Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers https://git.vgpu.io/open-iov.git/atom?h=master 2026-10-08T15:53:20+00:00 2026-10-08T15:53:20+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-08T15:53:20+00:00 urn:sha1:2ee4fe8f43b0dc3e080c91931eadade1fd636c27 Sweep of the 155 tracked C/Python/shell files under userspace/ (excluding the MIT-licensed vendored userspace/extern/), tools/ and scripts/ that had no per-file license identifier. Each gains the minimal two-line header in the area's existing form: 'SPDX-License-Identifier: BSD-3-Clause' plus 'Copyright (c) 2026 Open-IOV contributors'; shebang and coding lines stay first. No other content touched. kernel/** is deliberately out of scope (recorded as a follow-up in CODESTD-REPORT-2026-10-08.md): its SPDX coverage and MODULE_LICENSE normalization need their own GPL-2.0 pass. 2026-10-07T17:28:37+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T17:28:37+00:00 urn:sha1:a58eb29859c55fc38c30bc9433b5dfd16ae9e4d2 The real RM initialises every GPC's NV_PGPC_PRI_MMU_CTRL (0x500880 + gpc*0x8000) from NV_PFB_PRI_MMU_CTRL (0x100C80) using the TU102 hub-to-GPC matching fields (VM_PG_SIZE, COMP_FAULT, MISS_GRAN, CACHE_MODE, USE_PDB_BIG_PAGE_SIZE, ATOMIC_CAPABILITY_MODE, ATOMIC_CAPABILITY_SYS_NCOH; ext-tree gr_gk104.c:3340-3380 + gr_tu102.c:229-238). Our ladder never programmed it (grep-verified). The m93 INST dump shows the server's SC(0) PDB carries USE_VER2_PT_FORMAT + BIG_PAGE_SIZE=1, so a GPC/hub MMU_CTRL mismatch is a candidate for the GPC-side walker refusing the SM I-fetch with MMU_NACK while hub-side reads resolve. Gated by gsp_phys_rmcall_gr_gpc_mmu_init (default 0); sampler now reads GPC0/GPC1_MMU_CTRL (0x500880/0x508880) and PFB_MMU_CTRL (0x100C80). 2026-10-07T16:55:38+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T16:55:38+00:00 urn:sha1:3dd883f43c325f942b25be1accad82c7b431520c m90 decoded the TPC0 SM0 warp error as ESR.ERROR=0x20 ADDR_ERROR_TYPE=0xb = MMU_NACK (the ESR.ERROR field is an enum, not a bitmask). Add the 4R companion words (ESR_MASK 0x734, PC 0x738, PC_HI 0x73c) for GPC0/TPC0/SM0 and GPC1/TPC0/SM0 plus the per-GPC GPCMMU ESR at +0x324 so the next cycle captures the faulting PC and the MMU-side latch. 2026-10-07T16:48:02+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T16:48:02+00:00 urn:sha1:1052a4162a7b4440ed7b55cbebccebc5577ba0ee GPC0/TPC0 and GPC1/TPC0 raised the exception (GPC_EXCEPTION bit16 = TPC0 bitmap). SM warp ESR registers (TPC aperture = GPC base + 0x4000 + tpc*0x800; SM stride 0x80; ESR 0x730, INFO 0x76c) at 0x504730.. and 0x50c730.. carry the exact error code (ILLEGAL_INSTR_ENCODING 0x9, INVALID_CONST_ADDR_LDC 0x12, MMU_FAULT 0x17, MISALIGNED_PC 0x5, ...) plus the VEID/warp info. 2026-10-07T16:37:42+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T16:37:42+00:00 urn:sha1:9200f35a11df0c021c08f55fbc04e08ac7c702a6 PGRAPH_EXCEPTION bit24 (GPC) with EXCEPTION1 GPC1:0=0b11 fires at every forwarded QMD activation and the engine then saves/unloads. The per-GPC PRI window (BAR0 0x500000 + gpc*0x8000) carries NV_PGPC_PRI_GPCCS_GPC_EXCEPTION (0x2c90: PROP/ZCULL/GCC/SETUP/PES/TPC/GPCMMU0/GPCCS bits), GPC_ACTIVITY1.GPCMMU0 (0x2c84: FAULTED=6) and the GPCMMU GLOBAL_ESR (0x324): the post-mortem and the external sampler now record them to name the failing GPC sub-unit (or the GPC MMU). 2026-10-07T15:12:18+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T15:12:18+00:00 urn:sha1:26f0006adcb9dc83d41a3bf84f386892f33bde83 The m81 window still shows SEMAPHORE|EXCEPTION pending at QMD activation (the PM VA mapping did not clear it). NV_PGRAPH_EXCEPTION (0x400108) and its GPC/BE companions name which subunit raised the exception (FE/MEMFMT/PD/SCC/DS/ SSYNC/MME/SKED/GPC/BE), which discriminates an engine-context-restore fault from a method/instruction fault. 2026-10-07T15:05:24+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T15:05:24+00:00 urn:sha1:ab6fed7ee35a114541373af90184acde9bd94b6b The m75/m78/m79 launch windows show FECS_CTXSW_STATUS_FE_0.GR_INTR_REQ (bit17) asserted through the SKED CWD ACTIVE state and a following CTXSW_REQ (bit0) that results in the context save/unload. The real driver carries GR_INTR only transiently during its context load and clears it before ACTIVE. The PGRAPH interrupt latch (0x400100) names what the engine is signaling (e.g. ILLEGAL_METHOD bit4, SEMAPHORE bit1, NOTIFY); sampled by the external sampler and dumped in the launch post-mortem. 2026-10-07T14:16:41+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T14:16:41+00:00 urn:sha1:ea9130180949fd72eca534e4f5a83336ad7e5d4a The dispatch-time comparison against the live driver needs the GR context's floor-sweep state (CWD_FS expected 0x1806 on TU104) and the SKED debug interiors (HWW_INFO_1/2/3, CWD_T2, CACHE_0/1, L15_CACHE_0, TASKTABLE_0/1/2). Recorded 2026-10-07: the distro driver's executing steady state shows CWD_FS=0x1806, CWD_T0=0x3f002400 (VEID 63), SKED_ACTIVITY=0x600000c0, PGRAPH_STATUS=0x01242001, FECS_CURRENT valid and frozen for the kernel's lifetime, TASKTABLE zero. 2026-10-07T13:40:24+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T13:40:24+00:00 urn:sha1:d02b027e5293ad0213c8f9d0b31b93c47310bfa4 m72: append the vendor turingLocalMemUpdate block (SET_SHADER_LOCAL_MEMORY_A/B 0x790/0x794, NON_THROTTLED_A/B 0x2e4/0x2e8, WINDOW_A/B 0x7b0/0x7b4) to the forwarded GR launch prelude; without it the channel local-memory state is zero and the m64-m69 sampler shows SKED_HWW_ESR bit12 = SKEDCHECK05 LOCAL_MEMORY_TOTAL_SIZE latching while the CWD entry is allocated then deallocated. Base/per-TPC size are module params for A/B. m72: change-detecting SKED transition recorder in the launch poll (CWD_T0/1/2, HWW_INFO_1/2, ACTIVITY, HWW_ESR, GRFIFO, FECS current/new/ctxsw status) and extended post-mortem readbacks (HWW_ESR_EN, INFO_1/2/3, CWD_T2, watermarks). m72-r2 sampler result: the QMD enters SKED (CWD_T0=0x11300 STATUS=ACTIVE, CWD_T1=0x1070) and HWW_ESR stays 0 with the lmem block, but the FECS context load never completes: NEW_CTX=0x001f42b0 (V7 FBMEM instance, VALID=0) then CURRENT=0; the task frees (CWD_T0=0x12000 DEP=PENDING_TASK_COMPLETE). m63 (sysmem instance) had VALID=1 on the same load. m73 adds the sysmem instance/RAMFC selector (gsp_phys_rmcall_gr_inst_sys; default 0 = FBMEM capture shape) for the A/B. 2026-10-07T03:02:45+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-07T03:02:45+00:00 urn:sha1:00765678d59423669fcad6fe56cce9be9bb352e6 reg_sampler.py: high-rate read-only MMIO sampler for the physical GPU's PGRAPH/FECS/SKED/PFIFO registers (FECS current-context valid + pointer, SKED CWD table occupancy/activity, GRFIFO, FE QMD-virt, PMC_ENABLE) with analyze_regs.py for value distributions and transition timelines. Recorded ground truth and register semantics in tools/gr-regs/README.md. Used to capture the live distro-driver CUDA reference (FECS VALID=1, CWD table 0x3f002000 while running) and to observe the ladder's forwarded launch (CWD entry + SKED processing after the mode-35 lane enable).