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<title>open-iov.git/kernel/gsp_phys_vbios.c, branch dual</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=dual</id>
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<updated>2026-10-02T19:13:06+00:00</updated>
<entry>
<title>kernel: GR context-promote bisection modes 4-17 and server-managed-ctxbuf registry variant; complete vgsp rename; docs/tooling refresh</title>
<updated>2026-10-02T19:13:06+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-02T19:13:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=4bb8550a72597ec098c6d62a75006a0aba61972e'/>
<id>urn:sha1:4bb8550a72597ec098c6d62a75006a0aba61972e</id>
<content type='text'>
- gsp_phys_booter: GR promote bisection modes 4-17 (two-phase zero-field VA,
  batched entries, hVirtMemory, bare VA, KMD SKIP_CTXBUFFER_ALLOC channel,
  old-interface GPU_INITIALIZE_CTX, FBMEM context buffer, UVM-faithful PA-only,
  PATCH/PM auxiliary promotes, server-managed no-promote path); PATCH/PM
  geometry queries and buffers; pre-boot SET_REGISTRY profile selection
- gsp_phys_gpu: gsp_phys_rmcall_gr_promote clamp 0..17 and gsp_phys_srv_ctxbuf
  parameter; registry image variant with RMSetClientRMAllocatedCtxBuffer=0
- vgsp rename across kernel, scripts, tools and docs (module vgsp.ko,
  /sys/kernel/debug/vgsp/, vgsp-&lt;subsystem&gt;: log prefixes)
- risc-v-gsp-rm-debugger user-facing rename and docs/CI refresh; guest-diag
  tool updates; README/SBOM/install/Makefile sync

Live status: CE ladder and P6 guest-copy forwarding green; GR engine context
commit still open (all promote shapes accepted or cleanly refused; the channel
stays CTXNOTVALID) - see Handoff-vGPU-IO.md Addendum 21 (local).
</content>
</entry>
<entry>
<title>gsp-phys: correct the FWSEC interface-patch size and staging logging</title>
<updated>2026-10-01T11:27:10+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T11:27:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=17fb56cf38195a6a8ef8ed733b1ad53e0e9dd4ae'/>
<id>urn:sha1:17fb56cf38195a6a8ef8ed733b1ad53e0e9dd4ae</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: read-only FWSEC dry-run mode; match the 6-byte BIT token decode</title>
<updated>2026-10-01T11:22:09+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T11:22:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=e7c068e2e831c6c85e233578767fffe591876a88'/>
<id>urn:sha1:e7c068e2e831c6c85e233578767fffe591876a88</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: fix the WPR2-up release hand-back and tighten FWSEC/VBIOS checks</title>
<updated>2026-10-01T05:21:50+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T05:21:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=0055d732c38518bae3a0a58e8d4a6e427317ad8c'/>
<id>urn:sha1:0055d732c38518bae3a0a58e8d4a6e427317ad8c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: stage 3c FWSEC via VBIOS BIT image plus failure recovery</title>
<updated>2026-10-01T05:06:14+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T05:06:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=9a038702b1fc6ab867ebd3d6652ac3c7d04d6fff'/>
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