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<title>open-iov.git/kernel/gsp_phys_gpu.c, branch m32</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=m32</id>
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<updated>2026-10-06T19:41:01+00:00</updated>
<entry>
<title>vgsp: m32 rank-2 qmdwin - relocate the inline-QMD destination to a proven ring-chunk page (compile-verified, untested)</title>
<updated>2026-10-06T19:41:01+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:41:01+00:00</published>
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<id>urn:sha1:49f1853c8dfd0ad576561540219d835227af4b31</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: default the QMD-virt 0x29c pair off (m26 falsified it; non-vendor without BASE)</title>
<updated>2026-10-06T19:31:39+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:31:39+00:00</published>
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<id>urn:sha1:c15be05319e00d0818d78d6fdf908e27f19c659f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested)</title>
<updated>2026-10-06T19:31:07+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:24:42+00:00</published>
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<id>urn:sha1:cc69bf690814f927cdcbf1f5f6efeb0315a420c8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt 0x29c, w63 sentinel</title>
<updated>2026-10-06T19:19:54+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:19:54+00:00</published>
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<id>urn:sha1:dc5b6507889d07003cf01ed1d784c0faf48bec03</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + launch diagnostics</title>
<updated>2026-10-06T18:23:29+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T18:23:29+00:00</published>
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<id>urn:sha1:039daee13c5bac50919eff1ca26977ac49e37b06</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: mode-29 construct-last golden execution lane + fetch-aligned USERD control offset</title>
<updated>2026-10-06T17:35:23+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T17:35:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=61c2434533045524dfbb70e4d9aa82c08a5272db'/>
<id>urn:sha1:61c2434533045524dfbb70e4d9aa82c08a5272db</id>
<content type='text'>
- New mode 29 (GOLDEN_EXEC_LAST): identical to mode 28 but skips the
  TURING_COMPUTE_A alloc on the client-wired golden channel (every GR object
  construct there blocks RM); stage 3 completes with the golden handle
  swapped and BIND/GPFIFO_SCHEDULE/token are accepted. Param clamp 0..29.
- Shape bits: bit6 TSG parent (alloc accepted, same no-fetch), bit7 host
  USERD control offset 0 (THE FETCH FIX: the server applies the sysmem
  userd_mem base directly and ignores the captured USERD_INDEX_VALUE=3, so
  GP_PUT/GP_GET live at +0x8c/+0x88; m14: GP_GET advanced 1), bit8
  pre-promote compute object (invalid order: RM blocked -110 + NOCAT
  0x52a8b04).
- Failure diagnostics: REAL GR SEM FAILED now dumps both candidate USERD
  control offsets (ctl and alt).
</content>
</entry>
<entry>
<title>vgsp: golden-exec shape bisection + fwclient per-entry promotion + pool-VA stall fix</title>
<updated>2026-10-06T15:57:33+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T15:57:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=3f892b2924c0bdd15aaa04899b879601bd263981'/>
<id>urn:sha1:3f892b2924c0bdd15aaa04899b879601bd263981</id>
<content type='text'>
- Mode 28 golden execution lane behind gsp_phys_rmcall_gr_promote=28 with a
  shape bitmask (gsp_phys_rmcall_golden_exec_shape: ring / entries=8 / sysmem
  USERD / USERD size / hObjectBuffer=VAS / skip replay TURING_A) and a USERD
  control-offset helper. Finding: the RM-managed golden channel hangs any GR
  object construct (-110, no assert) as soon as client submission wiring
  (ring or sysmem USERD) is attached, so only the captured server-owned shape
  constructs; the machinery is kept for future wiring ideas.
- fwclient mask bit 11 (0x800): send each non-MAIN FWCLIENT promote entry as
  its own one-entry control and continue past refusals. V6 acceptance matrix:
  PM, PATCH, PRIV_ACCESS_MAP, UNRESTRICTED_PRIV_ACCESS_MAP accepted,
  FECS_EVENT refused 0x1f.
- fwclient mask bit 12 (0x1000): golden9 VA-only global bookings (BUNDLE_CB,
  PAGEPOOL, ATTRIBUTE_CB, RTV_CB_GLOBAL) accepted on V6; bits 13/14
  (0x2000/0x4000): FECS PA-only (refused 0x1f) and FECS VA-only (accepted).
- gsp_phys_rmcall_srv_main_ignore: ignore a server-reported MAIN in the
  srv-ctx commit and force the client INITIALIZE_CTX + VA-only fallback.
- gsp_sema_service: pool semaphores never fall back to the learned map; queue
  the absolute release via svc_pending_add until svc_pool_pa_resolve
  succeeds, and judge pool slots through the verified resolver in
  svc_apply_pending and the release decode (UVM registration stall fix).
</content>
</entry>
<entry>
<title>vgsp: mode 27 - golden9 context promote on the V6 execution channel only</title>
<updated>2026-10-06T12:01:32+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T12:01:32+00:00</published>
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<id>urn:sha1:4612968b4429c90e2df057f3d92d849e82d6342e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: add golden-replay mode 25 (captured client construct + atomic 9-entry promote)</title>
<updated>2026-10-05T21:16:18+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T21:16:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=fc8d7923c83c6babd0ee8c23565ac18b709fa5a5'/>
<id>urn:sha1:fc8d7923c83c6babd0ee8c23565ac18b709fa5a5</id>
<content type='text'>
Ladder mode 25 reproduces the real 570.144 host client's golden-image
construct on the golden replay handles: captured channel shape (flags
0x00200320, hObjectBuffer 0, gpFifoOffset 0, gpFifoEntries 0x20,
engineType 1, host memdesc substitutions), a single atomic 9-entry
GPU_PROMOTE_CTX on the golden channel (MAIN id0 and PATCH id2 combined,
ids 3/4/5/6 VA-only globals, ids 9/10/11 FECS/PRIV/UNR combined), then
the TURING_A 3D object. The golden VAS/channel/3D object stay alive and
the existing V6 FWCLIENT promote follows on the golden-initialized
GR-instance state; a failed golden step aborts with no retry and no
follow-up promote. The captured VAS COPY_SERVER_RESERVED_PDES control is
implemented gated (fwclient mask bit 8, zero-level no-op form) because
its level PAs are server-internal. Mode clamp/name/help extended to 25;
modes 1-24 unchanged.
</content>
</entry>
<entry>
<title>vgsp: FWCLIENT entry-selection mask and golden-replay hardening</title>
<updated>2026-10-05T20:04:33+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T20:04:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=7c1fceb5654cda3628531214934b93e96a507700'/>
<id>urn:sha1:7c1fceb5654cda3628531214934b93e96a507700</id>
<content type='text'>
- gsp_phys_rmcall_fwclient_mask (default 0x3f): per-entry selection for the
  mode-24 FWCLIENT promote set; bit6 selects the MAIN UVM VA-only shape.
- golden replay: tolerate the client-local system-memory PB step and continue
  with hObjectBuffer=0; on-ladder TURING_A 3D object retained best-effort.

Live bisection on the KMD channel: MAIN alone reaches the per-buffer commit
and stops at the engine-context memdesc state; PM-only and PATCH-only are
accepted; any multi-entry control containing MAIN is refused 0x1f. All
cycles release clean.
</content>
</entry>
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