open-iov.git/kernel/gsp_phys_gpu.c, branch cs-share Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers https://git.vgpu.io/open-iov.git/atom?h=cs-share 2026-10-06T23:34:01+00:00 vgsp: mode 34 - context-share golden execution lane (compile-verified, untested) 2026-10-06T23:34:01+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T23:34:01+00:00 urn:sha1:0be388f76468a99cec4bd88252d2fea4c3b5a70b Mode 34 allocates FERMI_CONTEXT_SHARE_A (0x9067) on the ladder TSG before the golden replay; the replay's golden channel A (0xcaf00054) attaches to the share with hVASpace=0 and keeps the captured unwired shape, runs its 9-entry promote and carries TURING_A (0xc597) plus a TURING_COMPUTE_A (0xc5c0, handle 0xcaf00090). V6 (0xcaf00034) attaches to the same share, constructs no class object of its own, and its FWCLIENT promote is suppressed; stage 4 and the forwarded launches run on V6 in A's shared VEID/subcontext. Default off; all paths gated by gsp_phys_rmcall_gr_promote=34. New pr_info cycle landmarks for the share alloc, A alloc/promote, A construct (rpc_result), V6 alloc and the instance/RAMFC decode. No hardware run. vgsp: mode 33 - wired golden sibling A as execution channel (compile-verified, untested) 2026-10-06T21:51:49+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T21:49:27+00:00 urn:sha1:789b145638daf452f550762ad3143fb8a73f1082 vgsp: SKED/FE readback + QMD w50..53 + two-step PCAS gate (m41 instrumentation) 2026-10-06T21:37:50+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T21:37:50+00:00 urn:sha1:930789eafcb2ed05929c5ca8f92b5fda3b58875c vgsp: m37 pcas gate (window-only stock form) + QMD w48..50 post-mortem 2026-10-06T21:05:16+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T21:05:16+00:00 urn:sha1:c8b9b89b15c334ea61e8fba635763e406e7b9f0c vgsp: m32 rank-2 qmdwin - relocate the inline-QMD destination to a proven ring-chunk page (compile-verified, untested) 2026-10-06T20:29:29+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T19:41:01+00:00 urn:sha1:191100b51d1e6ed36bf4ff776107d551c4793621 vgsp: default the QMD-virt 0x29c pair off (m26 falsified it; non-vendor without BASE) 2026-10-06T19:31:39+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T19:31:39+00:00 urn:sha1:c15be05319e00d0818d78d6fdf908e27f19c659f vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested) 2026-10-06T19:31:07+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T19:24:42+00:00 urn:sha1:cc69bf690814f927cdcbf1f5f6efeb0315a420c8 vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt 0x29c, w63 sentinel 2026-10-06T19:19:54+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T19:19:54+00:00 urn:sha1:dc5b6507889d07003cf01ed1d784c0faf48bec03 vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + launch diagnostics 2026-10-06T18:23:29+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T18:23:29+00:00 urn:sha1:039daee13c5bac50919eff1ca26977ac49e37b06 vgsp: mode-29 construct-last golden execution lane + fetch-aligned USERD control offset 2026-10-06T17:35:23+00:00 Arthur Hanson Rasmusson arthur@vgpu.io 2026-10-06T17:35:23+00:00 urn:sha1:61c2434533045524dfbb70e4d9aa82c08a5272db - New mode 29 (GOLDEN_EXEC_LAST): identical to mode 28 but skips the TURING_COMPUTE_A alloc on the client-wired golden channel (every GR object construct there blocks RM); stage 3 completes with the golden handle swapped and BIND/GPFIFO_SCHEDULE/token are accepted. Param clamp 0..29. - Shape bits: bit6 TSG parent (alloc accepted, same no-fetch), bit7 host USERD control offset 0 (THE FETCH FIX: the server applies the sysmem userd_mem base directly and ignores the captured USERD_INDEX_VALUE=3, so GP_PUT/GP_GET live at +0x8c/+0x88; m14: GP_GET advanced 1), bit8 pre-promote compute object (invalid order: RM blocked -110 + NOCAT 0x52a8b04). - Failure diagnostics: REAL GR SEM FAILED now dumps both candidate USERD control offsets (ctl and alt).