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<title>open-iov.git/kernel/gsp_phys_fwsec.c, branch master</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=master</id>
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<updated>2026-10-02T19:13:06+00:00</updated>
<entry>
<title>kernel: GR context-promote bisection modes 4-17 and server-managed-ctxbuf registry variant; complete vgsp rename; docs/tooling refresh</title>
<updated>2026-10-02T19:13:06+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-02T19:13:06+00:00</published>
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<id>urn:sha1:c9bf1cf098c8ea4daeb3e6c9b274a9025c03045d</id>
<content type='text'>
- gsp_phys_booter: GR promote bisection modes 4-17 (two-phase zero-field VA,
  batched entries, hVirtMemory, bare VA, KMD SKIP_CTXBUFFER_ALLOC channel,
  old-interface GPU_INITIALIZE_CTX, FBMEM context buffer, UVM-faithful PA-only,
  PATCH/PM auxiliary promotes, server-managed no-promote path); PATCH/PM
  geometry queries and buffers; pre-boot SET_REGISTRY profile selection
- gsp_phys_gpu: gsp_phys_rmcall_gr_promote clamp 0..17 and gsp_phys_srv_ctxbuf
  parameter; registry image variant with RMSetClientRMAllocatedCtxBuffer=0
- vgsp rename across kernel, scripts, tools and docs (module vgsp.ko,
  /sys/kernel/debug/vgsp/, vgsp-&lt;subsystem&gt;: log prefixes)
- risc-v-gsp-rm-debugger user-facing rename and docs/CI refresh; guest-diag
  tool updates; README/SBOM/install/Makefile sync

Live status: CE ladder and P6 guest-copy forwarding green; GR engine context
commit still open (all promote shapes accepted or cleanly refused; the channel
stays CTXNOTVALID) - see Handoff-vGPU-IO.md Addendum 21 (local).
</content>
</entry>
<entry>
<title>gsp-phys: freeze-safe release, boot-proof READY, and guest-wiring P2/P3/P5-wave1</title>
<updated>2026-10-02T06:07:52+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-02T06:07:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=c886760efda836b060fee03bfce852f16f04b5b8'/>
<id>urn:sha1:c886760efda836b060fee03bfce852f16f04b5b8</id>
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Host-freeze fix bundle (validated 2/2 supervised cycles):
- power unlock now latches D0/D3cold by default (new gsp_phys_repower,
  default 0); releasing the claim can no longer power-gate the board and
  hard-freeze the host on resume
- bounded post-rebind readiness gate before dropping the locks; bounded D0
  settle/verify before the unbind
- READY means a live GSP-RM session: the async worker and the module-owned
  join only expose READY when init-done is seen and no unload was sent;
  otherwise the claim is released fail-open
- FWSEC reads DMEM0/IMEM back before STARTCPU and fails fast when the
  staging is not visible
- the claim harness leaves the board latched by default and takes
  --restore-power to opt back into the old restore

Guest-wiring:
- P2: generation-keyed fn65 static-config snapshot cache plus a default-off
  identity overlay (new gsp_phys_static_live) for name/short-name/VBIOS;
  the probe cycle runs once per backend generation at READY
- P3: default-off read-only RM_CONTROL forwarding whitelist (new
  gsp_phys_ctrl_forward) with emulated-handle translation to the adopted
  server handles and full emulation fallback
- P5 wave 1: default-off shadow execution of guest CE pushes on the ladder
  channel (new gsp_phys_work_forward) via a dedicated ordered work item;
  the ladder stage-4 submission is refactored into a shared bounded helper
  and the software release path stays authoritative

Live: module-owned boot to init-done, guest smoke ALL OK 64/64 with P2/P3
enabled, 514 shadow copies observed on the physical CE; all cycles released
cleanly with WPR2 down and no reboot.
</content>
</entry>
<entry>
<title>gsp-phys: real GSP boot stages 3d/3e and the GSP-RM run-sequencer event</title>
<updated>2026-10-01T14:07:14+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T14:07:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=5f372957a5fd0dd7ca7d4b5f06e959cce92dd49e'/>
<id>urn:sha1:5f372957a5fd0dd7ca7d4b5f06e959cce92dd49e</id>
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Stage 3d stages the GSP-RM boot from host sysmem (FMC, radix3 over the GSP-RM ELF, signature, message queues, libos LOGINIT/LOGRM/RMARGS and GSP arguments) and runs Booter Load on SEC2: GSP RISC-V reset, libos mailbox, IMEM/DMEM direct load, BOOTVEC=0, M0==0, FALCON_OS, RISC-V active. Stage 3e links the status queue and polls for GSP-RM events; it now also executes the inline run-sequencer command buffer (event 0x1002) against BAR0 (REG_WRITE/MODIFY/POLL, DELAY, STORE, CORE_* including CORE_RESUME) and then waits for GSP_INIT_DONE 0x1001.

Gated by gsp_phys_boot / gsp_phys_boot_dryrun (default off; the normal load path writes nothing). gsp_phys_fwsec=1 without gsp_phys_boot=1 is refused: a FWSEC-only carve cannot pass the booter-unload handoff gate. Release quiesces the GSP, runs the existing FWSEC-SB/booter-unload teardown and frees all staging.

tools/gen_gsp_bindata.py decodes the public generated archives into the Booter Load image (prod signature patched at 0x8700) and the GSP-RM boot (FMC) image; both are self-checked at build time.
</content>
</entry>
<entry>
<title>gsp-phys: fix the booter-unload handoff seed (correct scratch register/access)</title>
<updated>2026-10-01T12:13:56+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T12:13:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=8f1187e6ebff5e2664d19e3e4c55af2e0f6205b4'/>
<id>urn:sha1:8f1187e6ebff5e2664d19e3e4c55af2e0f6205b4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: fix booter-unload teardown (WPR meta/args) so WPR2 is cleared on release</title>
<updated>2026-10-01T12:06:13+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T12:06:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=801d2051e464dbda44af94ff60587f9101314a4d'/>
<id>urn:sha1:801d2051e464dbda44af94ff60587f9101314a4d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: FWSEC failure diagnostics (falcon scratch/mailbox, DMEM/IMEM readback)</title>
<updated>2026-10-01T11:40:07+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T11:40:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=84ae1cff969c3ee72661ca85cf4ea2d23d9ac7ea'/>
<id>urn:sha1:84ae1cff969c3ee72661ca85cf4ea2d23d9ac7ea</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: correct the FWSEC interface-patch size and staging logging</title>
<updated>2026-10-01T11:27:10+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T11:27:10+00:00</published>
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<id>urn:sha1:9bbb199e574e9a219b144bc99ee02464139cb07a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: read-only FWSEC dry-run mode; match the 6-byte BIT token decode</title>
<updated>2026-10-01T11:22:09+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T11:22:09+00:00</published>
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<id>urn:sha1:aeb9e292925d8942a53f258416dea5de4218ec43</id>
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</content>
</entry>
<entry>
<title>gsp-phys: fix the WPR2-up release hand-back and tighten FWSEC/VBIOS checks</title>
<updated>2026-10-01T05:21:50+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T05:21:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=12db41d77c899400fffc0486b64ebd057a1e95fa'/>
<id>urn:sha1:12db41d77c899400fffc0486b64ebd057a1e95fa</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gsp-phys: stage 3c FWSEC via VBIOS BIT image plus failure recovery</title>
<updated>2026-10-01T05:06:14+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-01T05:06:14+00:00</published>
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<id>urn:sha1:b9264c40ad9f27f31176a9f8fe718196abde1800</id>
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