open-iov.git/kernel/gsp_phys_booter.c, branch m32reorder

vgsp: mode 32 - sibling A promote before V6 constructs (compile-verified, untested)

2026-10-06T20:00:41+00:00

vgsp: mode 31 sibling A userd memdesc (m28: TSG channel alloc rejected without it)

2026-10-06T19:52:25+00:00

vgsp: mode 31 FBMEM ctx + pre-PDB aux prepare (m27: sysmem MAIN hung the golden construct)

2026-10-06T19:50:58+00:00

vgsp: gate mode 31 on golden replay + physical backend (SA-CHK F1 fix)

2026-10-06T19:42:21+00:00

vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested)

2026-10-06T19:31:07+00:00

vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt 0x29c, w63 sentinel

2026-10-06T19:19:54+00:00

vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + launch diagnostics

2026-10-06T18:23:29+00:00

vgsp: install the Tier-2 scratch-pool window spine via PDE_UPDATE + IQ2M sentinel diagnostic

2026-10-06T17:47:57+00:00

- The Tier-2 shadow VAs (0x200000 + page<<21 + line<<16) had no PTE chain in the engine's table view on the shared-management VAS: pdb_build's client PD0 spine for the guest scratch PT pool is discarded by the server's root migration, so every param/program/release/alias leg the launch rewrites to a shadow VA was unreachable by the engine. Install each scratch pool window lazily through DMA_UPDATE_PDE_2 (same control shape as the Tier-1 installer, pool chunk as the leaf PT) the first time a shadow line in it is consumed; shared VAS only, idempotent via rmcall_guest_pt_win_mask. m17 confirmed the install is accepted (pdeIndex=1 VA 0x200000 status 0x0). - IQ2M sentinel: write 0xdeadbeef to the inline-QMD destination word 0 after the prewrite and report iq2m=ran/not-run in the post-mortem so 'engine stalled before the inline window' is distinguishable from 'QMD deposited but not executed' without a server capture.

vgsp: mode-29 construct-last golden execution lane + fetch-aligned USERD control offset

2026-10-06T17:35:23+00:00

- New mode 29 (GOLDEN_EXEC_LAST): identical to mode 28 but skips the TURING_COMPUTE_A alloc on the client-wired golden channel (every GR object construct there blocks RM); stage 3 completes with the golden handle swapped and BIND/GPFIFO_SCHEDULE/token are accepted. Param clamp 0..29. - Shape bits: bit6 TSG parent (alloc accepted, same no-fetch), bit7 host USERD control offset 0 (THE FETCH FIX: the server applies the sysmem userd_mem base directly and ignores the captured USERD_INDEX_VALUE=3, so GP_PUT/GP_GET live at +0x8c/+0x88; m14: GP_GET advanced 1), bit8 pre-promote compute object (invalid order: RM blocked -110 + NOCAT 0x52a8b04). - Failure diagnostics: REAL GR SEM FAILED now dumps both candidate USERD control offsets (ctl and alt).

vgsp: PRIV VA-only booking bit + verify the exact slot before consuming unreadable CE entries

2026-10-06T16:15:50+00:00

- fwclient mask bit 15 (0x8000): book the PRIV_ACCESS_MAP VA (the FWCLIENT entry form is init-only; the golden9 form carries the VA at VA_GOLDEN9_PRIV). Accepted on V6 (status 0), completing the maximal promoted context. - gsp_sema_service: svc_entry_want_reached() verifies the exact tracking slot against entry_want before the three unreadable-CE consume shortcuts treat the entry as delivered; when the slot lags, re-seed the expectation and let svc_fake_release author or queue the exact slot (UVM registration stall pair with the pool-VA verified-resolver queue).