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<title>open-iov.git/kernel/gsp_phys_booter.c, branch m32</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=m32</id>
<link rel='self' href='https://git.vgpu.io/open-iov.git/atom?h=m32'/>
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<updated>2026-10-06T19:41:01+00:00</updated>
<entry>
<title>vgsp: m32 rank-2 qmdwin - relocate the inline-QMD destination to a proven ring-chunk page (compile-verified, untested)</title>
<updated>2026-10-06T19:41:01+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:41:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=49f1853c8dfd0ad576561540219d835227af4b31'/>
<id>urn:sha1:49f1853c8dfd0ad576561540219d835227af4b31</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested)</title>
<updated>2026-10-06T19:31:07+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:24:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=cc69bf690814f927cdcbf1f5f6efeb0315a420c8'/>
<id>urn:sha1:cc69bf690814f927cdcbf1f5f6efeb0315a420c8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt 0x29c, w63 sentinel</title>
<updated>2026-10-06T19:19:54+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T19:19:54+00:00</published>
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<id>urn:sha1:dc5b6507889d07003cf01ed1d784c0faf48bec03</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + launch diagnostics</title>
<updated>2026-10-06T18:23:29+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T18:23:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=039daee13c5bac50919eff1ca26977ac49e37b06'/>
<id>urn:sha1:039daee13c5bac50919eff1ca26977ac49e37b06</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: install the Tier-2 scratch-pool window spine via PDE_UPDATE + IQ2M sentinel diagnostic</title>
<updated>2026-10-06T17:47:57+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T17:47:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=a8d4f128df384a4b5fb2fea2e2860112e38f9307'/>
<id>urn:sha1:a8d4f128df384a4b5fb2fea2e2860112e38f9307</id>
<content type='text'>
- The Tier-2 shadow VAs (0x200000 + page&lt;&lt;21 + line&lt;&lt;16) had no PTE chain
  in the engine's table view on the shared-management VAS: pdb_build's
  client PD0 spine for the guest scratch PT pool is discarded by the
  server's root migration, so every param/program/release/alias leg the
  launch rewrites to a shadow VA was unreachable by the engine. Install
  each scratch pool window lazily through DMA_UPDATE_PDE_2 (same control
  shape as the Tier-1 installer, pool chunk as the leaf PT) the first
  time a shadow line in it is consumed; shared VAS only, idempotent via
  rmcall_guest_pt_win_mask. m17 confirmed the install is accepted
  (pdeIndex=1 VA 0x200000 status 0x0).
- IQ2M sentinel: write 0xdeadbeef to the inline-QMD destination word 0
  after the prewrite and report iq2m=ran/not-run in the post-mortem so
  'engine stalled before the inline window' is distinguishable from 'QMD
  deposited but not executed' without a server capture.
</content>
</entry>
<entry>
<title>vgsp: mode-29 construct-last golden execution lane + fetch-aligned USERD control offset</title>
<updated>2026-10-06T17:35:23+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T17:35:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=61c2434533045524dfbb70e4d9aa82c08a5272db'/>
<id>urn:sha1:61c2434533045524dfbb70e4d9aa82c08a5272db</id>
<content type='text'>
- New mode 29 (GOLDEN_EXEC_LAST): identical to mode 28 but skips the
  TURING_COMPUTE_A alloc on the client-wired golden channel (every GR object
  construct there blocks RM); stage 3 completes with the golden handle
  swapped and BIND/GPFIFO_SCHEDULE/token are accepted. Param clamp 0..29.
- Shape bits: bit6 TSG parent (alloc accepted, same no-fetch), bit7 host
  USERD control offset 0 (THE FETCH FIX: the server applies the sysmem
  userd_mem base directly and ignores the captured USERD_INDEX_VALUE=3, so
  GP_PUT/GP_GET live at +0x8c/+0x88; m14: GP_GET advanced 1), bit8
  pre-promote compute object (invalid order: RM blocked -110 + NOCAT
  0x52a8b04).
- Failure diagnostics: REAL GR SEM FAILED now dumps both candidate USERD
  control offsets (ctl and alt).
</content>
</entry>
<entry>
<title>vgsp: PRIV VA-only booking bit + verify the exact slot before consuming unreadable CE entries</title>
<updated>2026-10-06T16:15:50+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T16:15:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=a1f9d3f7b77e954a1a9ee36c7f787fe2083b544a'/>
<id>urn:sha1:a1f9d3f7b77e954a1a9ee36c7f787fe2083b544a</id>
<content type='text'>
- fwclient mask bit 15 (0x8000): book the PRIV_ACCESS_MAP VA (the FWCLIENT
  entry form is init-only; the golden9 form carries the VA at VA_GOLDEN9_PRIV).
  Accepted on V6 (status 0), completing the maximal promoted context.
- gsp_sema_service: svc_entry_want_reached() verifies the exact tracking slot
  against entry_want before the three unreadable-CE consume shortcuts treat the
  entry as delivered; when the slot lags, re-seed the expectation and let
  svc_fake_release author or queue the exact slot (UVM registration stall pair
  with the pool-VA verified-resolver queue).
</content>
</entry>
<entry>
<title>vgsp: golden-exec shape bisection + fwclient per-entry promotion + pool-VA stall fix</title>
<updated>2026-10-06T15:57:33+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T15:57:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=3f892b2924c0bdd15aaa04899b879601bd263981'/>
<id>urn:sha1:3f892b2924c0bdd15aaa04899b879601bd263981</id>
<content type='text'>
- Mode 28 golden execution lane behind gsp_phys_rmcall_gr_promote=28 with a
  shape bitmask (gsp_phys_rmcall_golden_exec_shape: ring / entries=8 / sysmem
  USERD / USERD size / hObjectBuffer=VAS / skip replay TURING_A) and a USERD
  control-offset helper. Finding: the RM-managed golden channel hangs any GR
  object construct (-110, no assert) as soon as client submission wiring
  (ring or sysmem USERD) is attached, so only the captured server-owned shape
  constructs; the machinery is kept for future wiring ideas.
- fwclient mask bit 11 (0x800): send each non-MAIN FWCLIENT promote entry as
  its own one-entry control and continue past refusals. V6 acceptance matrix:
  PM, PATCH, PRIV_ACCESS_MAP, UNRESTRICTED_PRIV_ACCESS_MAP accepted,
  FECS_EVENT refused 0x1f.
- fwclient mask bit 12 (0x1000): golden9 VA-only global bookings (BUNDLE_CB,
  PAGEPOOL, ATTRIBUTE_CB, RTV_CB_GLOBAL) accepted on V6; bits 13/14
  (0x2000/0x4000): FECS PA-only (refused 0x1f) and FECS VA-only (accepted).
- gsp_phys_rmcall_srv_main_ignore: ignore a server-reported MAIN in the
  srv-ctx commit and force the client INITIALIZE_CTX + VA-only fallback.
- gsp_sema_service: pool semaphores never fall back to the learned map; queue
  the absolute release via svc_pending_add until svc_pool_pa_resolve
  succeeds, and judge pool slots through the verified resolver in
  svc_apply_pending and the release decode (UVM registration stall fix).
</content>
</entry>
<entry>
<title>vgsp: size the fwclient non-MAIN promote entries from the golden FBMEM aux buffers</title>
<updated>2026-10-06T12:08:33+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T12:08:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=b732be32aab408804c7759e0d08471c48b2763a5'/>
<id>urn:sha1:b732be32aab408804c7759e0d08471c48b2763a5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>vgsp: mode 27 - golden9 context promote on the V6 execution channel only</title>
<updated>2026-10-06T12:01:32+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T12:01:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.vgpu.io/open-iov.git/commit/?id=4612968b4429c90e2df057f3d92d849e82d6342e'/>
<id>urn:sha1:4612968b4429c90e2df057f3d92d849e82d6342e</id>
<content type='text'>
</content>
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