open-iov.git/docs/03-architecture/08-physical-gpu-integration.md, branch m33

docs: add the GR compute-launch frontier page and align execution status across the tree

2026-10-06T19:18:39+00:00

New page docs/04-implementation/03-execution-frontier.md describes the chain that must fire for a guest CUDA launch (guest push -> GPFIFO/front-end -> inline launch-descriptor install -> engine read/dispatch -> completion), where the leading edge is (the descriptor install path), how we know (front-end vs engine-authored observables and their limits), what is exonerated (context validity at dispatch, destination window mapping, fetch alignment, shared-buffer rule, parenting), the ranked issues (verbatim prelude targets, missing descriptor-virtualization control, sentinel hygiene), live investigation lines and labelled theories. Align every page that still said GR execution is blocked on engine-context validity to the current frontier, and add the new page to the README reading order (row 15, later rows renumbered). Docs only; no code.

kernel: GR context-promote bisection modes 4-17 and server-managed-ctxbuf registry variant; complete vgsp rename; docs/tooling refresh

2026-10-02T19:13:06+00:00

- gsp_phys_booter: GR promote bisection modes 4-17 (two-phase zero-field VA, batched entries, hVirtMemory, bare VA, KMD SKIP_CTXBUFFER_ALLOC channel, old-interface GPU_INITIALIZE_CTX, FBMEM context buffer, UVM-faithful PA-only, PATCH/PM auxiliary promotes, server-managed no-promote path); PATCH/PM geometry queries and buffers; pre-boot SET_REGISTRY profile selection - gsp_phys_gpu: gsp_phys_rmcall_gr_promote clamp 0..17 and gsp_phys_srv_ctxbuf parameter; registry image variant with RMSetClientRMAllocatedCtxBuffer=0 - vgsp rename across kernel, scripts, tools and docs (module vgsp.ko, /sys/kernel/debug/vgsp/, vgsp-: log prefixes) - risc-v-gsp-rm-debugger user-facing rename and docs/CI refresh; guest-diag tool updates; README/SBOM/install/Makefile sync Live status: CE ladder and P6 guest-copy forwarding green; GR engine context commit still open (all promote shapes accepted or cleanly refused; the channel stays CTXNOTVALID) - see Handoff-vGPU-IO.md Addendum 21 (local).

docs: engineering-operations playbook and project-wide status accuracy pass

2026-10-02T15:28:49+00:00

- docs/eng-ops.md gains Part II, live physical-backend engineering operations: hard rules, the full module-parameter matrix, the routine supervised cycle and clean-release checklist, the debugfs inventory, how to read gsp-phys-state, a debugging scenario catalogue (CTXNOTVALID/promote wedge, fail-safe WPR2, unload hangs, guest wedges, MMU/PTE and PBDMA faults, relay symptoms), a hazard register (crash causes and debugging side effects), the physical-backend OODA loop, and the work-context map with porting flows - architecture, implementation, operations, orientation, getting-started, portability, ecosystem and reference docs corrected to the current state: CUDA driver-API smoke green, CE-class work forwarding and engine-authored releases plus fault relay in place (default off), GR execution blocked on engine-context validity, the promote wedge and designed locked fail-safe, and P5 wave-2 subsumed - internal-reference cleanup in tracked docs (no analysis-source or local-archive references); historical architecture document bannered - README reading list and STATE-CURRENT frontier refreshed; new pages (runbook, green-eye user guide, porting sequence, porting/packaging notes) linked from the tree Link check: scripts/check-docs-links.py passes (56 files, no broken links).

gsp-phys: populate the chipset/CL block of the pre-boot system info

2026-10-01T19:35:35+00:00

Fill the GspSystemInfo chipset fields the production client syncs before the GSP boot instead of leaving them zero: - clPdbProperties (bitmask in the client's clSyncWithGsp order): bit 0 (config space accessible, from the OS MCFG/ECAM availability), bit 7 and bit 21 (Intel Skylake-family upstream-port setup: ASPM POR list, root-port nosnoop WAR), bit 13 (upstream port ASPM L1 capable), bit 27 (LTR supported+enabled up to the root port) and bit 32 (IO coherent). PDB_PROP_CL_UNSUPPORTED_CHIPSET is never assigned by the client, so the faithful unmatched-chipset value is 0. - Chipset = 0 (CS_UNKNOWN) for a host bridge with no chipsetInfo[] entry, the reference's no-match fallback. - FHBBusInfo/chipsetIDInfo: 10-byte BUSINFO blobs of the first host bridge of the GPU's domain (device, vendor, subdevice, subvendor, revision), with the subsystem-capability fallback on chipsetIDInfo. acpiMethodData is intentionally sent all-zero (bValid=0): no ACPI/AML calls are made and every consumer tolerates the no-data encoding. All device lookups use refcounted pci_get_device()/pci_dev_put().

gsp-phys: queue the pre-boot GSP_SET_SYSTEM_INFO and SET_REGISTRY async RPCs

2026-10-01T17:11:30+00:00

The real-GSP boot path staged the message queue but never queued the two fire-and-forget init RPCs the production client places in it before the booter starts. GSP-RM therefore created its GPU object without any system information and aborted RM init (live GSP_INIT_DONE rpc_result=0x59), with the resource-manager's object-database lookups asserting from the first journal record. Submit function 72 (GSP_SET_SYSTEM_INFO, 928-byte v17_00 payload carrying the BAR physical bases, domain/bus/slot, PCI IDs, the BAR0 config-mirror offset, link/FLR capabilities and upstream-port flags read from the pci_dev) and function 73 (SET_REGISTRY, header-only empty table, which the server explicitly accepts) through the existing submit-only queue producer after all stage-3d preconditions and before the GSP falcon reset/Booter Load kick. The wire layouts are re-declared in the module with per-field static asserts against the reference ABI; payloads are heap-allocated, so no new stack frames are introduced.

docs: record next-cycle readiness for the physical GSP boot

2026-10-01T14:40:54+00:00

STATE-CURRENT and the integration page reflect the implemented sequencer, clean-shutdown RPC and static-info probe awaiting the next supervised live cycle.

gsp-phys: command-queue TX and the GSP-RM unload RPC for clean teardown

2026-10-01T14:13:04+00:00

Adds a minimal msgq producer on the command queue (element layout, checksum, sequence, dma_wmb before writePtr, doorbell) and submits the UNLOADING_GUEST_DRIVER RPC so GSP-RM shuts down and sets the scratch14 handoff bit the Booter Unload gate needs. Release attempts the RPC once before quiescing when a boot ran; on-demand testing is available through the debugfs file gsp-phys-unload-rpc while the module owns the GPU. GSP-RM processor suspend is polled on the GSP mailbox.

docs: record the first real GSP boot and the live GSP-RM session

2026-10-01T14:07:15+00:00

STATE-CURRENT and the architecture docs now describe the observed order (FWSEC -> Booter Load -> RISC-V active -> event 0x1002 run-sequencer -> 0x1001 init-done), the four-handoff-bit clean-release constraint, and the --boot/--keep harness contract.

docs: record the board power-domain hazard and D0-lock mitigation for the physical backend

2026-10-01T04:04:25+00:00

- New 4.2: describe behaviourally how the option-D claim path can power-gate the board on driver release (platform power resource behind the root port, off/on sequence via the embedded controller), the two observed host freezes (no crash record), and the D0 lock now applied across release -> claim -> rebind: runtime-PM forbid + D3cold disable on the GPU, its board companion functions and the root port, config-space verification while claimed and again before rebind, abort with the locks held on any power-loss signature, runtime-PM restore after the distribution driver's probe. - 4.1/4.3: the lock is a required ownership step; returning to the normal driver is conditional, not assumed; real GSP boot not started. - 2/3(A): fresh no-unbind evidence - no exported RM/vGPU symbols and no manager daemon in the stock distribution build. - 6: driver-API baseline re-verified 64/64; ownership + firmware staging verified; power-domain lock implemented pending supervised verification. - 7/8: residual out-of-band power-cut risk, supervised-test requirement, and the gsp_phys_gpu + gsp_phys_hazard_ack operating constraint.

docs: execution-backend bring-up staged - ownership and firmware staging verified, real boot next

2026-10-01T03:12:09+00:00