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<title>open-iov.git/STATE-CURRENT.md, branch master</title>
<subtitle>Open-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
</subtitle>
<id>https://git.vgpu.io/open-iov.git/atom?h=master</id>
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<updated>2026-10-07T12:36:26+00:00</updated>
<entry>
<title>STATE-CURRENT: 2026-10-07 ~01:15 snapshot - 0xc5c0 construct GREEN + forwarded QMD enqueues/schedules; engine-core execution is the remaining wall</title>
<updated>2026-10-07T12:36:26+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-07T12:36:26+00:00</published>
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<id>urn:sha1:d6ca56771c49531e5e6160f97dbf94067a57a0af</id>
<content type='text'>
(a) The TSG+share lane's compute-object construct returns success after a
10-entry VA-only booking promote books the server's per-VAS ctx-buffer maps
(a mapped MAIN promote alone leaves them unbooked because the construct
skips its own mapping once MAIN is initialized).
(b) The forwarded guest QMD now enqueues and is scheduled: the missing
real-client step was the lane-enable tail (CILP preemption mode, timeslice
0x800, device scheduling enable); the front-end deposit, the scheduler CWD
entry (QMD id) and the engine-context load (VALID) all appear.
Register ground truth from the working distribution driver during live CUDA
plus the read-only sampler/analyzer are committed under tools/gr-regs/.
Remaining wall: the GR engine core does not execute the scheduled QMD (no
release written anywhere, no visible fault); ranked next moves in the
local handoff. Host clean, GPU green, no reboots.
</content>
</entry>
<entry>
<title>STATE-CURRENT: 2026-10-06 evening snapshot - TSG commit lane + IQ2M deposit proven, method space exhausted, structural levers next</title>
<updated>2026-10-06T23:24:10+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T23:24:10+00:00</published>
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<id>urn:sha1:a5473c91b8869b017385582ea969783b33553ded</id>
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</entry>
<entry>
<title>STATE-CURRENT: check-back snapshot (2026-10-06 10:57) - GR context partial acceptance, golden lane walled, engine dispatch still absent</title>
<updated>2026-10-06T14:57:17+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-06T14:57:17+00:00</published>
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<id>urn:sha1:333ee5389c514ce7d198b6624fc5fa1aaca22d9f</id>
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</entry>
<entry>
<title>STATE-CURRENT: 16:00 snapshot (GR golden replay, mode 24, FLR recovery)</title>
<updated>2026-10-05T19:58:47+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T19:58:47+00:00</published>
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<id>urn:sha1:9554ca1f344192e27bdc58e5b9ab1bd795e3be32</id>
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</entry>
<entry>
<title>STATE-CURRENT: 15:05 check-back snapshot (GR rung-2, mode 23 soft-stop, per-type VRAM live)</title>
<updated>2026-10-05T19:10:02+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T19:10:02+00:00</published>
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<id>urn:sha1:1f6d382c9f01d120b447b0a482241417a3b5e586</id>
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</entry>
<entry>
<title>STATE-CURRENT: 12:16 check-back snapshot (GR stage-4 frontier: PBDMA fetches GPGet=1, ctxsw fault 0x2c; 10 clean no-wedge cycles; GR fixes committed)</title>
<updated>2026-10-05T16:14:38+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T16:14:38+00:00</published>
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</entry>
<entry>
<title>STATE-CURRENT: hourly check-back snapshot (2026-10-05 12:12:01)</title>
<updated>2026-10-05T16:12:01+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T16:12:01+00:00</published>
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<id>urn:sha1:cf1041e7144db5ee87686fcd4ae9984c423f0a3c</id>
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</entry>
<entry>
<title>STATE-CURRENT: 10:38 check-back snapshot (campaign 239-242 green; 243b live; committed experiment e7ff3bf7)</title>
<updated>2026-10-05T14:39:31+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T14:39:31+00:00</published>
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<entry>
<title>STATE-CURRENT: 10:12 check-back snapshot (hold-all-unreadable experiment committed, module e7ff3bf7, campaign 239-262 validating)</title>
<updated>2026-10-05T14:15:49+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T14:15:49+00:00</published>
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<id>urn:sha1:e8e31431469f347b9dae8c0e33db23faafa51965</id>
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</entry>
<entry>
<title>STATE-CURRENT: 06:50 check-back snapshot + debugging-options catalogue</title>
<updated>2026-10-05T11:00:50+00:00</updated>
<author>
<name>Arthur Hanson Rasmusson</name>
<email>arthur@vgpu.io</email>
</author>
<published>2026-10-05T11:00:50+00:00</published>
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<id>urn:sha1:497778478b03fba81f5b2cb9a4eda938d62748be</id>
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Refresh the status page: the acceptance is holding under hardening (per-op once bitmap, epoch/content-hash gate, 15 s CE grace; first-attempt 86% -&gt; ~94-95%, fakes/run 3.39 -&gt; 0.61), the hold-all-unreadable experiment is live, and the residual classes are named (late-decode corruption, early UVM channel-manager stall, guest init panic). Add an options section listing candidate techniques that would accelerate debugging toward end-to-end CUDA (deterministic fault injection, offline pump model, structured host tracing, guest-memory forensics, GR-wall metadata/golden reference/static-analysis throughput, cheaper supervised cycles, concurrency checks, tooling automation) - explicitly not directives, each requiring an eng-ops admission record.
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