open-iov.git/STATE-CURRENT.md, branch lottery-m156-gate-attemptOpen-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
https://git.vgpu.io/open-iov.git/atom?h=lottery-m156-gate-attempt2026-10-14T19:52:51+00:00vgsp-gr: move win0 shadow pool clear of the data bounce window (matmul C rows 0..31)2026-10-14T19:52:51+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-14T19:52:51+00:00urn:sha1:857fe5f94f4554847b61592a544f3d7e22cdf1ee
m150 grew the GR data bounce window to 208 pages at main-PT slots
0x110..0x1df but left the win0 QMD shadow pool at VA 0x190000 (slots
0x190..0x197) - inside the new window. The win0 plant is unconditional on
every gsp_phys_rmcall_pdb_build() and runs after the one-shot bounce
plant, so it hijacked the PTEs for bounce pages 128..135, which hold the
first 8 pages of the third operand. victory_matmul's C rows 0..31
(8 pages x 256 floats = 8192 elements) were written into the shadow pages
and lost: MATMUL bad=8192, copy-out '56 changed by engine (first bi 136)'.
Move GSP_PHYS_RMCALL_VA_GR_SHADOW0_BASE to 0x1e0000 (slots 0x1e0..0x1e7),
directly above the last bounce/mail/marker page (0x1df000) and below the
0x200000 guest scratch window; both the plant and the launch-time shadow
VA derive from the macro. Add a static_assert so any future bounce growth
cannot silently re-introduce the overlap, and correct the stale slot-range
comments/logs (0x108..0x10f -> the current range).
Evidence: /tmp/opencode/dmesg-r143-mailmatmul.log (main PT[190..197] =
win0 chunk DMAs; 'window[160] reloc=0x1b0000 changed=1', 'window[128]
reloc=0x190000 changed=0'; MATMUL bad=8192). Live validation pending: a
fresh cycle's victory_matmul must print bad=0 STATUS OK.
STATE-CURRENT: 2026-10-14 status refresh (physical guest compute, ring fix, scrubber fix)2026-10-14T18:11:18+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-14T18:11:18+00:00urn:sha1:436c0f4a9b3cddfca677c57cbe3c4b652da0da17STATE-CURRENT: 2026-10-07 ~01:15 snapshot - 0xc5c0 construct GREEN + forwarded QMD enqueues/schedules; engine-core execution is the remaining wall2026-10-07T12:36:26+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-07T12:36:26+00:00urn:sha1:332be5337d49a45317a9b7e0381eb8f1749fbcb7
(a) The TSG+share lane's compute-object construct returns success after a
10-entry VA-only booking promote books the server's per-VAS ctx-buffer maps
(a mapped MAIN promote alone leaves them unbooked because the construct
skips its own mapping once MAIN is initialized).
(b) The forwarded guest QMD now enqueues and is scheduled: the missing
real-client step was the lane-enable tail (CILP preemption mode, timeslice
0x800, device scheduling enable); the front-end deposit, the scheduler CWD
entry (QMD id) and the engine-context load (VALID) all appear.
Register ground truth from the working distribution driver during live CUDA
plus the read-only sampler/analyzer are committed under tools/gr-regs/.
Remaining wall: the GR engine core does not execute the scheduled QMD (no
release written anywhere, no visible fault); ranked next moves in the
local handoff. Host clean, GPU green, no reboots.
STATE-CURRENT: 2026-10-06 evening snapshot - TSG commit lane + IQ2M deposit proven, method space exhausted, structural levers next2026-10-06T23:24:10+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:24:10+00:00urn:sha1:595dcded851dc45d78cc76280137100ea8b3d0adSTATE-CURRENT: check-back snapshot (2026-10-06 10:57) - GR context partial acceptance, golden lane walled, engine dispatch still absent2026-10-06T14:57:17+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T14:57:17+00:00urn:sha1:ba0954db862c3ffb7b098c10f6783ee9e42ec96aSTATE-CURRENT: 16:00 snapshot (GR golden replay, mode 24, FLR recovery)2026-10-05T19:58:47+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-05T19:58:47+00:00urn:sha1:9a8a48b71ddc868f2c52e36e8e4e2f622236054dSTATE-CURRENT: 15:05 check-back snapshot (GR rung-2, mode 23 soft-stop, per-type VRAM live)2026-10-05T19:10:02+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-05T19:10:02+00:00urn:sha1:d4b81d08e1f1aa01c5b6403f5dda3d5fc5c94e76STATE-CURRENT: 12:16 check-back snapshot (GR stage-4 frontier: PBDMA fetches GPGet=1, ctxsw fault 0x2c; 10 clean no-wedge cycles; GR fixes committed)2026-10-05T16:14:38+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-05T16:14:38+00:00urn:sha1:90576b7639fef1350d9173d8d682692cc2f7516fSTATE-CURRENT: hourly check-back snapshot (2026-10-05 12:12:01)2026-10-05T16:12:01+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-05T16:12:01+00:00urn:sha1:3ae7f57fd16b4c1850ad0a7dfffdb781f9bac14dSTATE-CURRENT: 10:38 check-back snapshot (campaign 239-242 green; 243b live; committed experiment e7ff3bf7)2026-10-05T14:39:31+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-05T14:39:31+00:00urn:sha1:a95798a12bcabd9f0a7bea3970b8cb2ab7984a6b