open-iov.git, branch v7-user-laneOpen-IOV vGPU-IO: host-side GSP emulation for unmodified NVIDIA guest drivers
https://git.vgpu.io/open-iov.git/atom?h=v7-user-lane2026-10-07T00:15:45+00:00vgsp: mode 35 - real-client user lane (TSG fault buffers, share, V7 channel, 3-entry PA-only promote, V7 execution swap; compile-verified, untested)2026-10-07T00:15:45+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-07T00:15:45+00:00urn:sha1:acceae05e5e6ccd15c27aca034d5f45d61e11b5b
Replays the decoded real 570.144 GSP client compute-context sequence on the
ladder, additive to modes 0-34:
- TSG fault-method buffers: one 0xa06c010a on the ladder TSG with two
0x2000 {base,size,alignment=1,addressSpace,cache} descriptors + zero
bar2Addr words + numValidEntries=2; server FBMEM first, registered host
sysmem fallback (capture order TSG -> faults -> share -> channel).
- FERMI_CONTEXT_SHARE_A (0x9067) reuse of the mode-34 helper (ladder TSG,
SHARED_MANAGEMENT VAS, flags SYNC -> VEID 0).
- V7 channel 0xcaf000a0: class 0xc46f, TSG parent, hVASpace=0, hContextShare,
captured flags 0x00201320 and internalFlags 0x1d, engineType 0, sysmem
hObjectError/errorNotifierMem, FBMEM instance/ramfc, sysmem USERD.
- One atomic 3-entry GPU_PROMOTE_CTX on V7 (MAIN/PM/PATCH, PA-only,
physAttr 4, bInitialize=1, bNonmapped=1) before any 0xc5c0 construct.
- TURING_COMPUTE_A (0xc5c0) on V7 after the accepted promote; execution
channel swapped to V7 for stage 4 BIND/SCHEDULE/token/GR-sem and
forwarding (V6 allocated but unscheduled; its promote suppressed).
- Mode-35-only golden9 entry refresh: FECS_EVENT attr=5 with the ctx-window
VA in the physAddr field, PRIV_ACCESS_MAP va=0/bNonmapped=1.
- gr_promote clamp/param doc extended to 0..35.
risc-v-gsp-rm-debugger: B5 two-task attach + aggregate-state decode + docs 51/53 status2026-10-06T23:57:20+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:57:20+00:00urn:sha1:23d8683f3012ac579db424735d1418814bb7ff01
- sim/libos_port.py: port-role model + two-task network (extintr handoff,
cross-task send/reply, TASK_STATE_QUERY trap state)
- sim/msgq_attach.py: image task discovery, bounded two-task schedule,
second-task-frontier divergence fields (first ring poll still blocked on
post-init resume + GSP_ARGUMENTS_CACHED handoff; no fabricated polls)
- harness/state_decode.py: aggregate 'group: key=value' state parsing
(20-gsp-phys-state-* dumps) + kv diff classification
- tests: 127 green across the five observability modules
- docs/51/53: status and changelog updates
vgsp: mode 34 - add GOLDEN_CTXSHARE to the GR ctx FBMEM MAIN selector (m46 sysmem MAIN hang class)2026-10-06T23:49:28+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:49:28+00:00urn:sha1:9de2a2a9899236b62b413ceb78946778fc6ada39vgsp: add read-only gsp-phys-reg-probe debugfs register snapshot2026-10-06T23:46:02+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:45:12+00:00urn:sha1:315bec1caf0d949d83cb31e2908590ed6665b19f
Add a read-only BAR0 register-liveness probe at
/sys/kernel/debug/vgsp/gsp-phys-reg-probe that prints "name addr value"
for the PMC chip-id/clock gate, PGRAPH status/fault, SKED/HWW and
FECS/GPCCS falcon state, the front-end QMD virtual-window controls and
the GSP context registers, followed by decoded field lines.
Read-only (readl only); additive to gsp_phys_boot_debugfs_init(); no
ladder logic changed. Used to distinguish a clock/power-gated engine
from a halted or running one during a physical cycle.
vgsp: mode 34 - context-share golden execution lane (compile-verified, untested)2026-10-06T23:46:02+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:34:01+00:00urn:sha1:fb658fb1101aee3f2597ff22bdf33b0d3bfb0b0a
Mode 34 allocates FERMI_CONTEXT_SHARE_A (0x9067) on the ladder TSG before the
golden replay; the replay's golden channel A (0xcaf00054) attaches to the share
with hVASpace=0 and keeps the captured unwired shape, runs its 9-entry promote
and carries TURING_A (0xc597) plus a TURING_COMPUTE_A (0xc5c0, handle
0xcaf00090). V6 (0xcaf00034) attaches to the same share, constructs no class
object of its own, and its FWCLIENT promote is suppressed; stage 4 and the
forwarded launches run on V6 in A's shared VEID/subcontext. Default off; all
paths gated by gsp_phys_rmcall_gr_promote=34. New pr_info cycle landmarks for
the share alloc, A alloc/promote, A construct (rpc_result), V6 alloc and the
instance/RAMFC decode. No hardware run.
risc-v-gsp-rm-debugger: land docs 45-53 + harness/sim tool set with tests2026-10-06T23:28:39+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:28:39+00:00urn:sha1:6c3fd5df61ff2f5cb8833ead6c05eaff9fdc92bf
rm_capture (chunked decode), launch_audit, state_seed/state_decode,
valprobe, rehost, contracts+run_contracts, host_traffic, gmmu_walk,
msgq_attach, libos_port, log_decode, server_snapshot; doc index updates
in the tool overview, operations pages and the repo README.
STATE-CURRENT: 2026-10-06 evening snapshot - TSG commit lane + IQ2M deposit proven, method space exhausted, structural levers next2026-10-06T23:24:10+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T23:24:10+00:00urn:sha1:a5473c91b8869b017385582ea969783b33553dedvgsp: mode 33 construct A object pre-promote (m43 post-promote 0x57)2026-10-06T21:55:05+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T21:55:05+00:00urn:sha1:556739301fe8c5387171b1513ddff8d5da551a9cvgsp: mode 33 - wired golden sibling A as execution channel (compile-verified, untested)2026-10-06T21:51:49+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T21:49:27+00:00urn:sha1:789b145638daf452f550762ad3143fb8a73f1082vgsp: SKED/FE readback + QMD w50..53 + two-step PCAS gate (m41 instrumentation)2026-10-06T21:37:50+00:00Arthur Hanson Rasmussonarthur@vgpu.io2026-10-06T21:37:50+00:00urn:sha1:930789eafcb2ed05929c5ca8f92b5fda3b58875c