open-iov.git, branch m32reorder

vgsp: mode 32 - sibling A promote before V6 constructs (compile-verified, untested)

2026-10-06T20:00:41+00:00

vgsp: mode 31 sibling A userd memdesc (m28: TSG channel alloc rejected without it)

2026-10-06T19:52:25+00:00

vgsp: mode 31 FBMEM ctx + pre-PDB aux prepare (m27: sysmem MAIN hung the golden construct)

2026-10-06T19:50:58+00:00

vgsp: gate mode 31 on golden replay + physical backend (SA-CHK F1 fix)

2026-10-06T19:42:21+00:00

vgsp: default the QMD-virt 0x29c pair off (m26 falsified it; non-vendor without BASE)

2026-10-06T19:31:39+00:00

vgsp: mode 31 - D-golden-first TSG-sibling ordering (compile-verified, untested)

2026-10-06T19:31:07+00:00

vgsp: m26 GR launch discriminator - rebuilt window (prelude off), QMD-virt 0x29c, w63 sentinel

2026-10-06T19:19:54+00:00

docs: add the GR compute-launch frontier page and align execution status across the tree

2026-10-06T19:18:39+00:00

New page docs/04-implementation/03-execution-frontier.md describes the chain that must fire for a guest CUDA launch (guest push -> GPFIFO/front-end -> inline launch-descriptor install -> engine read/dispatch -> completion), where the leading edge is (the descriptor install path), how we know (front-end vs engine-authored observables and their limits), what is exonerated (context validity at dispatch, destination window mapping, fetch alignment, shared-buffer rule, parenting), the ranked issues (verbatim prelude targets, missing descriptor-virtualization control, sentinel hygiene), live investigation lines and labelled theories. Align every page that still said GR execution is blocked on engine-context validity to the current frontier, and add the new page to the README reading order (row 15, later rows renumbered). Docs only; no code.

vgsp: TSG-sibling mode 30, UVM-stall Patch C, QMD shadow-window ensure + launch diagnostics

2026-10-06T18:23:29+00:00

vgsp: install the Tier-2 scratch-pool window spine via PDE_UPDATE + IQ2M sentinel diagnostic

2026-10-06T17:47:57+00:00

- The Tier-2 shadow VAs (0x200000 + page<<21 + line<<16) had no PTE chain in the engine's table view on the shared-management VAS: pdb_build's client PD0 spine for the guest scratch PT pool is discarded by the server's root migration, so every param/program/release/alias leg the launch rewrites to a shadow VA was unreachable by the engine. Install each scratch pool window lazily through DMA_UPDATE_PDE_2 (same control shape as the Tier-1 installer, pool chunk as the leaf PT) the first time a shadow line in it is consumed; shared VAS only, idempotent via rmcall_guest_pt_win_mask. m17 confirmed the install is accepted (pdeIndex=1 VA 0x200000 status 0x0). - IQ2M sentinel: write 0xdeadbeef to the inline-QMD destination word 0 after the prewrite and report iq2m=ran/not-run in the post-mortem so 'engine stalled before the inline window' is distinguishable from 'QMD deposited but not executed' without a server capture.